Phase-independent digital correlator for use in radar systems

ABSTRACT

A phase independent digital correlator for use in radar systems comprising a signal input circuit, a multiplying stage, a plurality of combination devices, an integrating circuit, a plurality of threshold devices and a signal output circuit. The multiplying stage comprises at least one pair of 90* phaseshifted multipliers. The combination devices, coupled between the multipliers and the integrators, form linear combinations of the product signals produced by the multipliers. The threshold circuit comprises a plurality of inputs that are coupled to separate integrators.

United States Patent 51 3 689 750 Esser 1 Sept. 5, 1972 [54] PHASE-INDEPENDENT DIGITAL [56] References Cited CORRELATOR FOR USE IN RADAR SYSTEMS UNITED STATES PATENTS 3,388,398 6/1968 Kratzer et al. ..343/17.5 [72] g g gggx gzg fgi 3,514,585 /1970 Norsworthy ..235/l81 3,553,722 1/1971 Ott ..235/18l X [73] Assignee: U.S. Philips Corporation, New

York, NY. Primary Examiner-Felix D. Gruber 22 Filed: Dec. 14, 1970 Awmekmnk [21] Appl. No.: 97,624 [57] ABSTRACT A phase independent digital correlator for use in radar Foreign Application Priority Data systems comprising a signal input circuit, a multiplying stage, a plurality of combination devices, an integrat- 1969 Netherlands "6918338 ing circuit, a plurality of threshold devices and a signal output circuit. The multiplying stage comprises at [52] g i; 235/156 least one pair of phase-shifted multipliers. The 3 l /9 343/5 D 343/ combination devices, coupled between the multipliers and the integrators, form linear combinations of the a; meet -571f 52i5 by the 235/150.52, 150.53; 343/17.1, 17.5, 5, 5 DP, CL

threshold circuit comprises a plurality of inputs that are coupled to separate integrators.

4 Claims, 6 Drawing Figures PATENTEDsEP 5 I972 3.689.750

sum 2 or 4 IXVEXTOR.

LEONARD J. M. ESSER PHASE-INDEPENDENT DIGITAL CORRELATOR FOR USE IN RADAR SYSTEMS The invention relates to a phase-independent correlator comprising in order of succession a signal input, a multiplying stage, an integrating stage, to which a threshold device is connected, and a signal output. The multiplying stage includes at least one pair of 90 phase-shifted multipliers, each of which is connected to the signal input and to at least one source of comparison signals. 7

Such an arrangement is shown in Dutch Pat. No. 6706096. In the digital embodiment of this arrangement the two binary output signals of the multiplying stage are directly applied to the individual counters. These counters count the difference between the number of and l values of these binary signals. The states of the counters area measure for the correction of the incoming signal by the comparison signals, one counter state being proportional to the sin and the other to cos wherein d is a phase angle depending upon the phase of the incoming signal. In order to obtain a phase-independent output signal from the correlator, these counting results, as stated in said Patent Application, have to be further processed in the same manner as in the analogue embodiment in squaring devices and in an adder.

It is also known to determine the amplitude of an analogue signal of arbitrary phase but with projections given on two mutually perpendicular axes, by the formation of linear combinations of the projections. For this purpose, one of the projections is multiplied in a combination device by the values cos(21ri/n), where i= 1,2 n, and the other projection is multiplied by the values sin(21r i/n), where i= 1,2 n. These products are obtained with the aid of resistance networks constructed, for example, as otentiometers. By adjustment of the sliding contacts of the-potentiometers the cosine and sine values by which the projections of the analogue signal are multiplied, are accurately obtained. Subsequently, the products formed by the multiplications of the projections by the cosine and sine values, containing the same index i, are summed in pairs in an adder, and in a threshold device the larger of these sum signals isdetermined. The value of the sum signal thus selected is a measure of the amplitude of the analogue signal.

The invention provides a novel concept of the production of a phase-independent output signal of a digital correlator.

The phase-independent correlator in accordance with the invention is characterized in that between the multiplying stage and the integrating stage, signal combination devices are provided for the formation of linear combinations of the product signals provided by the multipliers, each of these signal combination devices being connected to a separate integrator. The threshold device has a plurality of input and each integrator is connected to a separate input of the threshold device. The coefficients of the linear combination formed by the i" combination device (i 1,2 n) are formed by integral numbers, which are the numerators of two fractions having equal denominators, said fractions being approximately .cos 21ri/n and sin 211' ill: respectively. The threshold device has a threshold value at the corresponding i"' input, which is equal to a constant value of all inputs multiplied by the denominator of said fractions.

This correlator has the advantage that it can be constructed from simple digital circuits.

The invention and its advantages will be described more fully with reference to embodiments shown in FIGS. 2-6.

Identical parts are designated in the various Figures by the same references.

FIG. 1 shows a known correlation radar system.

FIG. 2 shows a first embodiment of the correlator embodying the invention for use in the radar system of FIG. 1.

FIG. 3 is a vector diagram for explaining the operation of the correlation in accordance with the invention.

FIG. 4 shows a second embodiment of the correlator in accordance with the invention.

FIG. 5 is a graph of the accuracy of the threshold approximation and FIG. 6 shows a third embodiment of a correlator in accordance with the invention.

FIG. 1 shows a known correlation radar system comprising a code generator R(t). The output signal thereof is applied on the one hand to a shift register 8,, the outputs of which deliver the signal after a period of time 1 270, m and on the other hand to a modulation stage MZ. To this modulation stage is also applied a high-frequency carrier cos Qt, the phase of which is modulated in this modulation stage by the signal from the code generator R(t). This phase-modulated signal is transmitted via the transmitter aerial ZA. A portion of the energy from reflections from objects at different distances and at different speeds is captured together with noise by the receiver aerial OA. The receiver has to be capable of selectively discriminating the energy originating from the reflection from an object of a given speed and a given distance. For this purpose the incoming signal is applied to two mixing stages M0 and M0 To the mixing stage M0 is furthermore applied a signal cos (0- o)t and to'the mixing stage M0 is applied a signal sin(Q- o)t Therein w designates an artificial Doppler frequency, which serves to prevent the higher harmonics of the lowest potential Doppler frequencies in the signal from producing erroneous indications. The phase-shifted signals are applied to analog-digital converters (AD), which convert the signals, for example, into pulse-widthmodulated signals appearing at discrete instants.

Correlators are used as selective elements. The radar system comprises identical, multiple correlators CI in an array of rows and columns. The number of rows is determined by the distance intervals to be distinguished (n) and the number of columns is determined by the number of speed intervals to be distinguished (m). The numbers, n, m are integral numbers and are determined as follows: if e.g. the radar device has a range of miles and the distance intervals are chosen to be half a mile each, then n 200, and if the speed range is 1,000 miles an hour and the speed intervals are chosen to be 5 miles an hour each, thenvn =200.

For each speed interval a sine and a cosine generator Do with the required Doppler frequency W are provided.

Six signals are applied to each of the correlators. For example, the correlator CL, receives a signal from the code generator R(t) with a time lag x1 by the shift register S at the input terminal 1 and at the input terminals 2 and 3 the two pulse-width-modulated signals from the analog-digital converters (AD) and at the input terminals 4 and 5 the sine and cosine signals from the Doppler generator D0,, which signals are clipped by means incorporated in the Doppler generators with a view to the digital processing in the correlator Cl The terminals 6 receive pulse sequences having pulse repetition frequencies largely exceeding those of the discrete instants of the pulse-width modulation, said sequences being used for controlling the correlators. A pulse width modulated signal can be transformed into a pulse number modulated signal by scanning the pulsewidth modulated signal at regular times to generate a pulse every time as the pulse-width modulated signal has a high value at a scanning time. The number of generated pulses in the repetition time of the pulsewidth modulated signal is a measure of the pulse-width. To obtain an accurate transformation the scanning frequency must be several times higher than the pulse repetition time (discrete instants) of the pulse-width modulation. Before further explaining the correlators it should be noted that analog signals may also be applied to the correlators and that the analog-digital conversion may be performed in the correlator.

FIG. 2 shows the correlator C1,, of the matrix of identical correlators of the radar system illustrated in FIG. 1.

The correlator CI, comprises a known multiplying stage V, a combination stage C, an integrating stage I and a threshold device Dr. The Figure, moreover, shows a control-stage S, which controls the correlator Cl and which is common to a plurality of correlators. The multiplying stage represented by the block V comprises four identical multipliers represented by blocks A B A and B The circuitry of block A comprises four and-gates E to E each having four input terminals e, to e,. Inverters (represented by circles in the Figure) are connected between the terminals 2 and e, of the and-gate E and the terminals of the and-gate E between the terminals e and e of the and-gate E and the terminals of the and-gate E and between the terminals e and e, of the and-gate E, and the terminals of the and-gate E The terminals 2 of all and-gates are connected to each other and to an input terminal operating as a connecting terminal of the block A Likewise the terminals e e;, and e are connected to the connecting terminals 7, 8 and 9. The connecting terminals 7 of the multiplying blocks are connected to each other and to terminal 1 of the correlator CI The connecting terminals 8 of the blocks A and A' are connected to each other and to the connecting terminal 2 of the correlator C1 The connecting terminals 8 of the blocks 8,, and 8' are connected to each other and to the connecting terminal 3 of the correlator CI The connecting terminal 9 of the block A is connected through an inverter to the connecting terminal 9 of block B and to the input terminal 5 of the correlator CI The connecting terminals 9 of the blocks A}, and B are connected to each other and to the input terminal 4 of the correlator CI The terminals 10 of the blocks A to B' are connected to the input terminals 6a to 6d of the correlator CI The outputs of the and-gates E, to E of block A are connected to each other and to the output terminal U of block A The output terminals U of the blocks A and B are connected to the inputs of the or-gates 0,, the output terminal p of which may be considered to form the multiplying stage V. Likewise the output terminals u of the blocks A, and B,,- are connected to the inputs of an or-gate 0 the output terminal q of which may be considered to form a second output terminal of the multiplying stage V.

The control-stage S comprises a first, synchronous divide-by-two circuit TW having output terminals 11 and 12, to which a clock pulse in the form of a pulse sequence is applied via the control-terminal St which is connected to the input terminal K. The output terminals 11 and 12 of the divide-by-two circuit TW are connected to the inputs of a second synchronous divide-by-two circuit TW the control-terminal S1 of which is connected to the input terminal K, said circuit having output terminals 21 and 22. The control-stage S comprises furthermore six and-gates S 1 to S The input terminal K of the control-stage, the output terminal 11 of the divide-by-two circuit TW, and the output terminal 22 of the divide-by-two circuit TW are connected via separate input terminals to the gate 5,. The input terminal K of the control stage and the output terminals 12 and 22 are connected to separate input terminals of the gate S The input terminal K of the control-stage and the output terminals 11 and 21 are connected to separate input terminals of the gate S The input terminal K of the control-stage and the output terminal 21 and the output terminal 12 are connected to separate input terminals of the gate S The output terminals of the and-gates S to S, are connected to the input terminals 6a to 6d. The control-stage supplies pulses to these input terminals, i.e. the first to the input terminal 6a, the second to the input terminal 6b, the third to the input terminal 6c, the fourth to the input terminal 6d and the fifth to the input terminal 6a etc. These pulses are applied to the and-gates of the multipliers A B A and B In dependence upon the sign of the product signals in the multiplier formed from the signals applied to the terminals 1 to 5 of the correlator Cl at the instant of application of a pulse via an input terminal 10 to l of the multipliers, this pulse is or is not delivered by the relevant multiplier at the output terminal u. The pulses appearing at the output terminals u of the multipliers are consecutive in time; in this case serial processing is contemplated. The pulses appearing at the output terminals u, and u of the multipliers A and B are delivered via the or-gate 0 at the output terminal p. Likewise the pulses appearing at the output terminals u and u, of the multipliers A' and B are delivered via the or-gate 0 at the output terminal q. The signals appearing at these terminals are consequently formed by modulated pulse sequences p and q respectively, termed binary signals hereinafter.

The sum of the values 1" minus the sum of the values 0 of these binary signals is, after a given time (termed correlation time) a measure for the amplitude of the specific incoming signal originating from a reflection from an object located at a distance corresponding to the time lag x1' /2 and having a speed corresponding to the Doppler frequency (w r-we). multiplied by the cosine and the sine respectively of the phase angle qb depending upon the phase of the incoming signal.

This is illustrated in the vector diagram of FIG. 3. The specific incoming signal R having a phase angle (1) is decomposed along the xand y-axes of a rectangular co-ordinate system into the components p, and q,,, which represent the binary signals at the terminals p and q of the multiplying stage In the known arrangement the difference between the numbers of 1 and values of the binary signals at the terminals p and q is continuously counted separately for each terminal and squared, the two square values being added to each other. The resultant numerical value is proportional to the amplitude of the specific incoming signal and hence proportional to the length of the vector R in the vector diagram of FIG. 3. Squaring and adding of digital signals are time-consuming and expensive processes. The invention has for its object to avoid squaring and to determine the amplitude of the specific incoming signal in a simple manner. The principle and operation of the correlators will be described more fully with reference to the vector diagram of FIG. 3.

The rectangular co-ordinate system comprises an axis L, going through the origin and being at an angle 111 to the x-axis. The projection of p on this axis is P,, and equal to P COSlII and the projection of q, on this axis is Q, and equal to q sin :11. The projection ofR on this axis is R, and equal to P Q so that R,, =p, cos 1!: q, sin :11 with p R cos i]: and q R sin 11: provides this R,,= R cos i]; |J1. By providing a plurality of axes being at equal angles to each other and by determining the projections of R on these axes and be assessing the projection of the greatest length the length of the vector R is approached. With an n-axes system the maximum value of (lli lll) =1T/(2n).

The maximum relative error is then R R /R (l cosrr/Zb). With a two-axes system this error is 29 percent, with a three-axes system this error is 13.4 percent, with a four-axes system it is 7.6 percent and with a sixaxes system it is even not more than 3.4 percent.

The binary signal p at the output terminal p of the multiplying stage V has to be multiplied in accordance with the formula for R in n separate signal combination devices by the values of cos 21rj/n (j l, n). Likewise the binary signal q has to be multiplied in these n separate signal combination devices by the values of sin 21rj/n. However, the sine and the cosine of real angles provide results lying between 0 and 1, which renders digital processing difficult. The invention obviates this difficulty by approaching sin (21rj/n) by 'vUuj Uj and the cos (21rj/n) by wherein u,- and v, are integers. The numbers of bits of the binary signals p, and q, are multiplied in the signal combination devices by u and v, respectively. The resultant bit numbers from the signal combination devices are applied per signal combination device to the individual counters, which determine the difference between the numbers of l and 0" values of the bit numbers. However, these results are a factor 1/ u v higher These counter positions are transferred to a threshold device, which assesses whether a given counter position (termed threshold value) is exceeded, after which an output signal is delivered for indicating the presence of an object in a given distance interval and inside a given speed interval. By choosing threshold values a factor Vufi v} higher than the counters which deliver a count that is also a factor u v} higher, these high counts are corrected in a simple manner.

The invention will be explained more fully with reference to a four-axes system illustrated in FIG. 5.

The multiplication factors of this four-axes system are indicated in Table A for the binary signals p, and q,.

The first column indicates the angles between the four axes and the x-axis. Columns 2 and 3 indicate the desired exact multiplication factors for the binary signals p and q,. Columns 4 and 5 indicate the real multiplication factors and column 6 indicates the threshold values. Therefore the combination stage C of FIG. 2 is constructed as follows: the output terminals p and q of the multiplying stage V are connected to the input terminals of the combination stage C. For multiplying the binary signal p, by l and the binary signal q, by 0, the input terminal connected to terminal p is directly connected to the output terminal c of the combination stage C. Likewise, for multiplying the binary signal p by 0 and the binary signal q, by l, the input terminal connected to the output terminal q is directly connected to the output terminal 0 of the combination stage C. For multiplying the binary signal p by l and the binary signal q by l the two input terminals are connected to the input terminals of a first or-gate Oc the output terminal of which is directly connected to the output terminal c of the combination stage C. For multiplying the binary signal p, by -l and the binary signal q, by 1 the input terminal connected to terminal p is connected via an inverter to an input terminal of an and-gate EC, the other input terminal of which is connected to the input terminal 63 of the correlator CI The output terminal of this and-gate is connected to an input terminal of a second or-gate 00 and the other input terminal of the combination stage C is directly connected to a second input terminal of the or-gate 0C2. The output terminal of the or-gate is directly connected to the output terminal 6, of the combination stage C. The four output terminals c to c of the combination stage are connected to the respective inputs of four identical counting devices TL, to TL, of the integrating stage I. The counting device TL, shown in some detail in FIG. 2 comprises a forward and a backward counter T,, which counts forwardly when a pulse is applied to the input and counts backwardly when a pulse is applied to the input. The input is connected to the output terminal of a first and-gate ET, and the input is connected to the output terminal of a second and-gate ET The output terminal 0, of the combination stage C is directly connected to an input terminal of the and-gate ET, and via an inverter to an input terminal of the and-gate ET,. The other input terminal of the gate ET,, termed the control-terminal, is connected to the other input terminal (termed controlterminal) of the gate ET, and is connected to the input terminal 6g of the correlator CI Likewise the control-terminals of the counting device TL, and of the counting device TL, are connected to the input terminal 6f of the correlator Cl, and the control-terminals of the counting device TL, are connected to the input terminal 6e of the correlator CI The input terminal 6g is connected to the output of the and-gate S of the control-stage S. An input terminal of the gate 8,, is connected to the input terminal K of the controlstage S and a further input terminal is connected to an output terminal 22 of the divide-by-two device-Tw It is thus ensured that the and-gates of the counting device TL, can deliver a pulse only when they receive a significant signal originating from the binary signals of the multipliers A and B In the same manner the input terminal 6e is connected to the output terminal of an and-gate S of the control-stage S. An input terminal of this gate S is con nected to the input terminal K of the control-stage S and a further input terminal is connected to the output terminal 21 of the divide-by-two circuit TW The counting device TL, can therefore count only the signal value at the input terminal of this counting device at the instants when the multipliers A and B deliver a significant signal.

The input terminal 6f is directly connected to the input terminal K of the control-stage S. The counting device TLn and the counting device TL, can thus count the significant signal values of the bits of the binary signals delivered by all multipliers A to B', of the multiplying stage V.

It will be obvious that the counting device will be activated by the value of the signal at the input terminals at the instant of reception of a control-pulse. If said value corresponds to l the counting device will add and if said value corresponds to 0 the counting device will subtract. Multiplication by l means that, when the sign of the product signal formed by the input signals in the multipliers A',, and B' is positive at the instant of delivery of a control-pulse, this pulse has to be subtracted from the contents of the counting device and conversely. This may be achieved by means of a simple inverter, as is indicated at an input terminal of the and-gate E0 of the combination stage C.

The output terminals of the counting devices TL, to TL, of the integrating stage I are connected to the input terminals of a threshold device Dr. This device compares the absolute positions of the counters T, and T with the value D and those of the counters T and T, with a value of D 2 The latter threshold is chosen w/Ttimes higher due to the H excess quantity of bits at the output terminals 0 and c, of the combination stage C. The threshold device Dr delivers a signal at the output terminal 14,, when one of the counting devices exceeds the threshold value associated therewith. These threshold values are rounded off to an integral number. It should be noted that the and-gates of the counting devices may be dispensed with by differently organizing the multipliers A to B' For this purpose each multiplier has to be provided with two output terminals, one output terminal delivering a pulse when the product signal formed by the input signals at the terminals 7 to 10 is positive and one output terminal U delivering a pulse when the product signal formed by said signals is negative for each kind of output terminal an individual combination device C is then required, which are identical for each pair of output terminals. The counters may then be free running counters, the inputs of which are connected to one of the combination devices C, the inputs being connected to the other combination device C.

As an alternative, control-signals may be applied to the counting devices alone without being applied to the multipliers. This requires completely separate paths for the signals emanating from the multipliers.

The arrangement shown in FIG. 2 has the disadvantage that the counters of the counting devices TL, and TL, have to be suitable for counting a w/Ttimes higher value than the counters TL, and TL,. However, it is possible to divide by two the values to be counted by the counting devices TL, and TL, For this purpose the multiplying stage V has to be controlled in a different manner. This embodiment of the arrangement in accordance with the invention is illustrated in FIG. 4. Hereinafter only the differences between the arrangements of FIG. 2 and 4 will be dealt with.

The control-stage S comprises an input terminal K, which is connected to the control-terminal St of a divide-by-two circuit TW,, which has the output terminals 11 and 12. The control-stage comprises, in addition, two and-gates S, and 8,. One of the input terminals of the and-gate S, is connected to the input terminal K of the control-stage and the other is connected to the output terminal 11 of the divide-by-two circuit TW,. One of the input terminals of the and-gate S is connected to the input terminal K of the control-stage and the other input terminal is connected to the output terminal 12 of the divide-by-two circuit TW The output terminal of the and-gate S, is connected to the input terminal 6a of the correlator Cl and the output terminal of the and-gate S is connected to the input terminal 6b of the correlator CI At the terminals 6a and 6b alternatively appear the pulses of the clock pulse signal applied to the input terminal K of the control-stage S.

The most important difference from the arrangement shown in FIG. 2 consists in that the input terminals 10 of the multipliers A A and B respectively, B' are connected to each other and to the input terminals 6a and 6b of the correlator CI It is thus ensured that the bits of the binary signals p and q, respectively are delivered at the terminals p and q respectively of the multiplying stage V, which is termed parallel processing.

The projections on the four axes are again obtained by means of the multiplication factors indicated in columns 4 and 5 of Table A. The projection on the axis being at an angle 17/4 to the x-axis is detailed in Table B.

TABLE B to be counting Use of p, l q, I counted result and-gates l l l +21 l l l l 0 0 l 0 +1 l 0 0 0 0 l l 2 I If the two outputs p and q of the multiplying stage deliver binary signals of high value, p, and q 8 have the values 1". This is indicated in the first line of the columns 1 and 2; there has to be counted 1 "+1 so that as a result the contents of the counter are increased by +2(see column 4). If at one of the two outputs p and q the binary signal is low, so that p, or q has the value 0, there has to be counted 0+ 1", the result being zero as is indicated on lines 2 and 3 of Table B. If at the two outputs p and q the binary signals are low, the counting result'is 2, as is indicated on line 4 of Table B. As is indicated in the last column the measuring results may be divided by 2 so that counters of lower capacity may be employed. This is achieved by using and-gates in the combination stage C of the kind described with reference to FIG. 4.

The output terminals p and q are directly connected to the input terminals of a first and-gate Ec and through inverters to the input terminals of a second and-gate Ec of the combination stage C. The output terminal of the gate B0 is directly connected to the output terminal 0 and the output terminal of the gate Ec is directly connected to the output terminal 0 of the combination stage C. It is thus achieved that only when the two binary signals p and q s are high a pulse is delivered at the output terminal c and when the two binary signals p and q s are low, a pulse is delivered at the output terminal 0' The output terminal 0 is directly connected to the pulse counting input of the counter T and the output terminal 0' is directly connected to the minus-counting input of the counter T The counting device TL thus comprises only the counter T The output of the counter T is connected to the threshold device Dr, whose required threshold value has to be chosen a factor 2 lower than that indicated in FIG. 2.

In the same manner the arrangement determining the projection on the axis being at an angle of 31r/4 to the x-axis can be simplified. The output terminal p of the multiplying stage is connected through an inverter to an input of a third and-gate E0 of the combination stage C. The output terminal q is directly connected to the other input terminal of this and-gate. The output terminal of this gate Ec is connected to the output terminal c of the combination stage C, said output terminal being directly connected to the -linput of the counter T of the counting device TL which is constructed in the same manner as the counting device TL The output terminal p is directly connected to the input terminal of a fourth and-gate Ec of the combination stage C. The output terminal q is connected through an inverter to the other input terminal of this gate E0 The output terminal of this gate EC, is connected to the output terminal c of the combination stage C. The terminal C' is directly connected to the minus-input of the counter T The output terminal of this counter is connected to the threshold device Dr, whose threshold value required for this counter has to be chosen a factor 2 lower than that shown in FIG. 2. The arrangement of the further axes has not been changed, only the control-terminals of the counters T and T are connected to the input terminal 6c of the correlator CI said input terminal being connected to the input terminal K of the control-stage S.

The parallel process has the advantage that counters of lower counting capacity will suffice, the and-gates of some counters may be omitted, the control-stage S of the correlators CI is simple and the counting rate may be doubled. This double counting rate increases the permissible bandwidth of the signals to be correlated. The accuracy of a four-axes system as compared with the known result obtained by squaring is illustrated in FIG. 5 in a vector diagram.

The four axes being at an angle of O, 1r/4, 1r/2 and 31r/4 respectively to the x-axis are designated in the Figure by a to a An input signal R having a phase angle 4) is also represented.

It is supposed that, if the correlation result provides a value exceeding a given threshold value D it is stated with great certainty that this result originates from the reflection of an object and is not provided only by the summation of noise.

The threshold value D is represented in FIG. 5 by a circle of a radius D. The threshold values of the threshold device Dr of FIGS. 2 and 4 are represented in this Figure by the lines D, to D It should be noted that the threshold device compares both a positive and a negative counting result with the same absolute threshold value. From FIG. 5 it will be apparent that the desired threshold circle may be represented by approximation by an external regular octagon. A better approximation is obtained by a regular polygon having 2n angles by using n axes in a regular array over 2w. By using a plurality of axes, in most cases sin 21rj/n and cos 21rj/n can be approached only by fractions, the numerators u, and v, of which are large numbers because the exact values of the sine and the cosine result in roots in the numerators of the fractions. However, high values of u,- and v require devices comprising counters of very high counting capacity, which is expensive. The invention obviates this disadvantage by using an axis system not completely regularly distributed over 217. This is illustrated by an embodiment as shown in FIG. 6. This embodiment comprises a six-axes system with serial processing. Hereinafter only the differences between the arrangements of FIG. 2 and 4 will be dealt with. The control-stage S comprises three divide-bytwo circuits TW to TW The input terminal K of the control-stage is connected to the control-terminals St of all divide-by-two circuits TW to TW The divideby-two circuit TW comprises output terminals 11 and 12, which are connected to the input terminals of the divide-by-two circuit TW having output terminals 21 and 22. The output terminals 21 and 22 are connected to the input terminals of the divide-by-two circuit TW having output terminals 31 and 32. Four and-gates S to S are provided, each having four input terminals. The first input terminal of gate S' is connected to the input terminal K of the control-stage. The second input terminal is connected to the output terminal 11; the third input terminal is connected to the output terminal 22 and the fourth input terminal is connected to the output terminal 32. The input terminals of the gate S' are connected in the same manner to the input terminals K the output terminal 11, the output terminal 21 and the output terminal 31. The input terminals of the gate S, are connected likewise to the input terminal K, the output terminal 11, the output terminal 21 and the output terminal 32 and the input terminals of the gate S, are connected in the same manner to the input terminal K, the output terminal 11, the output terminal 21 and the output terminal 31. Each of the outputs of these gates is connected to a separate one of the input terminals 6a to 6e of the correlator C1 Each of the input terminals 6a to 6c is connected to a separate control-terminal of the multipliers A B A' and B (not shown). For this purpose the multipliers A and B can deliver a signal at the output terminal p of the multiplying stage V at the instants of appearance of the (l 8n)" pulse and the (5 8n pulse of the clock signals applied to the input terminal K of the control-stage S (n 1, 2, 3, Likewise the multipliers A' and 8' are adapted to deliver a signal at the output terminal q of the multiplying device V at the instants of appearance of the (3 8n)" pulse and the (7 8n)" pulse of the pulse sequence applied to the input terminal K of the control-stage S (n l, 2,

The multiplying factors of this six-axes system are indicated for the binary signals p, and q in Table C.

The angles between the axes and the x-axis are indicated in column 1. Columns 2 and 3 indicate the exact values of the cosine and sine multiplication factors.

Because 3 is not appropriate for digital processing and in order to avoid processing with multidecimal numbers as an accurate approximation of V3, which requires devices having counters of high counting capacity, [3 is approximately represented by the nearest integral number, that is to say 2. Columns 4 and 5 of Table C indicate the multiplication factors, for which this approximation is used, for the binary signals p, and q Column 6 indicates the associated threshold values. Owing to the approximation the axes are at angles of 26 30' and 63 30' respectively to the -axis instead of being at angles of 30 and 60 respectively.

The arrangement of the combination stage of this sixaxes system is represented in the block C. The output terminal p is directly connected to the output terminal 0, of the combination stage C. Likewise the output terminal q is directly connected to the output terminal c, of the combination stage C in order to obtain a multiplication of the binary signals p, and q s by a factor 1.

The combination stage C comprises two identical multiplying devices TV, and TV Such a multiplier, which has to multiply the number of bits of the binary signals by 2, comprises a storage element F and four and-gates T, to T The storage element is a bistable circuit F. The inputs thereof are connected to the output terminals of the and-gates T, and T The output terminals of the bistable circuit F are connected to the input terminals of the and-gates T and T.,. The input terminal of the gate T, is connected to the terminal p of the multiplying stage V and the other input terminal is connected to the input terminal 6i of the correlator CI An input terminal of gate T is connected to the output terminal of the portion P of the bistable circuit F and the other input terminal is connected to the input terminal 6 of the correlator CL The other input terminal of the gate '1, is connected to the input terminal 6j and the other input terminal of the gate T, is connected to the input terminal 6i of the correlator C1 The output terminals of the and-gates T and T, are connected to the input terminals of an or-gate T The input terminal 6i of the correlator C1,, is connected to the output terminal of an or-gate S, of the controlstage S. An input terminal of the gate S, is connected to the output terminal of the and-gate S,. A further input terminal is connected to the output terminal of the and-gate S,. The input terminal 6j of the correlator Cl is connected to the output terminal of the and-gate S, of the control-stage S, of which a input terminal is connected to the input terminal K of the control-stage S and a further input terminal is connected to the output terminal 12 of divide-by-two circuit TW, a third input terminal being connected to the output terminal 21 of the divide-by-two circuit TW,. It is thus ensured that at the instants of appearance of the (l 4n)"' pulse (n 1, 2, 3 of the clock pulse sequence applied to the input terminal K of the control-stage these pulses are applied to the input terminal 6i of the correlator and at the instants of appearance of the (2 4n)" pulses (n 1, 2, 3 of the clock pulse sequence applied to the input terminal K of the controlstage these pulses are applied to the input terminal 6j of the correlator. The operation is as follows: At the instants of appearance of the (l 4n)" pulses a pulse is delivered or not delivered at the terminal p of the multiplying stage in accordance with the sign of the product signal, which pulse is applied together with the pulse at the terminal 6i of the and-gate T, of the multiplier TV,. This will transfer the signal value at the output terminal of the gate T, to the input of portion F of the bistable circuit F. Thus the output of the portion F, of the bistable circuit F will take over said value. This signal value of the output terminal of F together with the pulse at the input terminal 6i, is applied to the andgate T.,, which transfers said value to an or-gate T This value of the signal at the output of F is, moreover, applied to the input terminal of the and-gate 1 At the instant of appearance of the (2 4n)" pulses a pulse is supplied at the other input terminal of the gate T The input value of the signal at the first input terminal of gate T is then applied to the input terminal of F The output of the portion F will take over this signal value. The signal value at the output of F,, together with the pulse at the input terminal 6j, is transferred to the and gate T This and-gate passes the signal value to an input terminal of the or-gate T Because the output terminals of the and-gates T and T, are never equally high, the or-gate T, will pass the signal values at said instants.

The arrangement of the second multiplier TV is identical. However, this multiplier receives other pulses from the control-stage, i.e. via the input terminals 6m and 6k of the correlator.

The input terminal 6m is connected to the output terminal of the or-gate S' of the control-state. A first input terminal of said gate is connected to an output of the and-gate S and a second input terminal is connected to the output of S;,. Thus terminal 6m receives the (3+4n)" pulses (n l, 2, of the clock pulse sequence applied to the input terminal K of the controlstage.

The input terminal 6k-is connected to the output of the and-gate S' of the control-stage S. A first input terminal of this gate is connected to the input terminal K and a second input terminal is connected to the terminal 12 of the divide-by-two circuit TW and a third input terminal is connected to the output terminal 22 of the divide-by-two circuit TW of the control-stage S. Thus the (4 4n) pulses (n 1, 2, of the clock pulse sequence applied to the input terminal K are delivered at terminal 6K.

By this control the multiplier TV will deliver at its output terminal the signal value at the instants of appearance of the (3 4n)" pulses of the clock pulse sequence at terminal q of the multiplier V at the instants coinciding with the (3 4n)" and the (4 4n)" pulses (n l, 2, of the clock pulse sequence.

The output terminal of the multiplier TV is connected to a first input terminal of an or-gate O, and through an inverter to a first input terminal of an andgate E',, the other input terminal of which is connected to the output terminal of an or-gate A first input terminal of this or-gate is connected to the input terminal 6i and the other input terminal of the or-gate O is connected to the input terminal 6j of the correlator CI The output terminal of the and-gate E is connected to a first input terminal of the or-gate 0,. The output terminal of the multiplier TV is connected to a first input terminal of an or-gate O and to a first input terminal of an or-gate 0 The output terminal p of the multiplying stage V is connected to the other input terminal of the or-gate O and via an inverter to an input terminal of the and-gate E';, the other input terminal of which is connected to the output terminal of an or-gate 0 The input terminal of this or-gate O is connected to the input terminal 6k and a further input terminal of this gate is connected to the input terminal 6m of the correlator CI The output terminal of the and-gate E is connected to the other input terminal of the or-gate 0 The output terminal q of the multiplying stage V is connected to the other input terminal of the or-gate O and of the or-gate 0 The output of the or-gate O is connected to the output terminal 0 of the combination stage C. The output terminal of the gate 0 is connected to terminal 0 the output terminal of gate 0 is connected to terminal 0 and the output terminal of O, is connected to the terminal 0 of the combination stage C.

The bits appearing at the output terminals 0 to c are composed of the products of the factors indicated in the columns 4 and 5 of Table C for the binary signals p and q,.

The terminals c, to C are connected to individual counting devices TL to TL of the integrating stage I.

The significant signals appearing at the input of the counter TL, coincide with the (l 4n)"' pulses of the clock pulse sequence applied to the input terminal K of the control-stage S. The control-terminal of the counting device TL, is connected for this purpose to the input terminal 6e, which is connected to the output terminal of the or-gate S,,, which delivers these pulses at said instants. The significant signals appearing at the input of the counters TL TL coincide with the (l 4n pulse, the (2 4n)"' pulse and the (3 4n)" pulse (n l, 2, of the clock pulse sequence applied to the input terminal K of the control stage S. The control-terminals of the counters TL 2 and TL are connected for this purpose to the input terminal 6h. This input ter minal is connected to the output terminal of the or-gate S An input terminal of this gate S' is connected to the output terminal of the or-gate 8' a further input terminal is connected to the output terminal of the gate 8' and a third input terminal is connected to the output terminal of the and-gate 8' so that at said instants pulses are delivered at the input terminal 6h.

The significant signals appearing at the input of the counter TL;, and of the counters TL coincide with the (l 4n)", the (3 4n)"' and the (4 4n)"' pulses (n l, 2, of the clock pulse sequence applied to the input terminal K of the control-stage S. The controlterminals of the counters TL and TL are connected for this purpose to the input terminal 6g. This input terminal is connected to the output terminal of the or-gate S An input terminal of this gate S' is connected to the output terminal of the or-gate S',,, a second input terminal is connected to the output terminal of the orgate 8' and a third input terminal is connected to the output terminal of the andgate S' so that at said instants pulses are delivered at the input terminal 63.

The significant signals appearing at the input of the counter TL coincide with the (3 4n)"' pulses of the clock pulse sequence applied to the input terminal K of the control-stage S. The control-terminal of the counter TL is connected for this purpose to the input terminal 6f, which is connected to the output terminal of the or-gate S which delivers said pulses at said instants. The threshold of the threshold device Dr are, in connection with the corrections formed by the term u} v,- for the six counters in order of succession D, D

What is claimed is:

l. A phase independent digital correlator comprising signal input means for receiving digital signals, circuit means comprising at least one pair of phase-shifted multiplying devices coupled to said signal input means for forming products of the digital signals, a plurality of combination devices coupled to said multiplying means for forming linear combinations of said product signals, the coefficients of the linear combination formed by the i'" combination device (i=l,2,3, n) being integral numbers, said integral numbers being the numerators of two fractions having equal denominators, said fractions being approximately cos 2rri/n and sin 27ri/n, integrating circuit means comprising a plurality of integrating devices for determining the values of the linear combinations of said product signals, each integrating device being connected to a separate signal combination device, threshold circuit means comprising a plurality of inputs, each of said inputs being connected to a separate integrating device for correcting the value of the linear combination of the product signals, said threshold circuit means having a threshold value at the corresponding i'" input equal to a constant value of all inputs multiplied by the denominator of said fractions, and signal output means coupled to said threshold circuit means for providing an output signal proportional to the amplitudes of said digital signals.

2. A phase independent correlator as claimed in 

1. A phase independent digital correlator comprising signal input means for receiving digital signals, circuit means comprising at least one pair of 90* phase-shifted multiplying devices coupled to said signal input means for forming products of the digital signals, a plurality of combination devices coupled to said multiplying means for forming linear combinations of said product signals, the coefficients of the linear combination formed by the ith combination device (i 1,2,3, . . . n) being integral numbers, said integral numbers being the numerators of two fractions having equal denominators, said fractions being approximately cos 2 pi i/n and sin 2 pi i/n, integrating circuit means comprising a plurality of integrating devices for determining the values of the linear combinations of said product signals, each integrating device being connected to a separate signal combination device, threshold circuit means comprising a plurality of inputs, each of said inputs being connected to a separate integrating device for correcting the value of the linear combination of the product signals, said threshold circuit means having a threshold value at the corresponding ith input equal to a constant value of all inputs multiplied by the denominator of said fractions, and signal output means coupled to said threshoLd circuit means for providing an output signal proportional to the amplitudes of said digital signals.
 2. A phase independent correlator as claimed in claim 1, wherein said 90* phase-shifted multiplying device comprises and-gates and inverters.
 3. A phase independent correlator as claimed in claim 1, wherein said signal combination device comprises and-gates and bistable circuits.
 4. A phase independent correlator as claimed in claim 1, wherein each integrating device comprises a counter. 